Japan’s Rapidus 2nm Plan Challenges Nvidia as Big Tech Races for AI Chips
Table of Contents
TL;DR
- Nvidia still controls ~80 % of AI-chip shipments, leaving little room for alternatives.
- Google’s Ironwood TPU is now openly offered for inference workloads on Google Cloud.
- Rapidus aims to mass-produce 2 nm chips by 2027 but only $6.5 bn of $35 bn required is subsidized.
- Single-wafer processing gives customization but hurts volume throughput – a critical trade-off for the two-year ramp-up.
- Talent pipelines in Japan have thinned since the 1990s; hiring engineers now costs 30 % more than in the US.
Why this matters
When I walked into the data-center boardroom last year, the CFO asked why we ever considered an alternative to Nvidia’s H100. The answer was simple: cost, supply-chain fragility, and a strategic need to avoid a single-vendor lock-in. Nvidia’s ~80 % share of the AI-chip market — a figure quoted across analyst reports — means any disruption ripples through every AI-heavy workload we run. The emerging “second tier” of accelerators—Google’s Ironwood, Amazon’s Trainium, Microsoft’s Maia, and the ambitious Japanese 2 nm project Rapidus—promise new levers for cost, energy efficiency, and geographic diversification. Yet each comes with its own set of technical and financial hurdles that can decide whether they become a real option or just a headline.
Core concepts
| AI Chip | Primary Use Case | Key Limitation |
|---|---|---|
| Nvidia H100 | Data-center training & inference, multi-tenant clouds | Power-hungry, expensive, limited customization |
| Google Ironwood TPU | Large-scale inference on Google Cloud | Closed ecosystem, only Google-managed deployments |
| Amazon Trainium | Custom AI workloads on AWS | Proprietary, not open to on-prem customers |
| Microsoft Maia | Azure-native AI services | Restricted to Microsoft stack |
| Rapidus 2 nm (planned) | Next-gen AI accelerator for domestic and OEM markets | Still in pilot, funding gap, talent shortage |
Sources: “Nvidia — CNBC (2024)”, “Google — Ironwood TPU (2025)”, “IBM — Rapidus and IBM (2025)”
- Market dominance: Nvidia holds roughly 80 % of AI-chip shipments — a figure that has been stable since the launch of the H100 Nvidia — CNBC (2024).
- Google’s Ironwood: Introduced at Google Cloud Next 2025, Ironwood is the seventh-generation TPU, designed solely for inference and advertised as “the most powerful, capable and energy-efficient TPU yet” Google — Ironwood TPU (2025).
- Rapidus funding: The Japanese government has pledged over US $6.5 bn in subsidies for Rapidus, which represents only about one-fifth of the projected US $35 bn total spend Kyodo News — Japanese government to invest (2025).
- EUV cost: State-of-the-art EUV lithography tools from ASML cost > $300 M each, a capital hurdle that any sub-3 nm fab must absorb.
- Nanosheet transistors: IBM’s nanosheet-gate-all-around (GAA) technology is the fundamental building block of Rapidus’ 2 nm node IBM — Rapidus and IBM (2025).
- Pilot line: Rapidus powered up a pilot production line in April 2025, marking a crucial step toward volume.
How to apply it
Map your workload profile.
- Identify which kernels dominate your AI stack (e.g., matrix multiplication, tensor-core ops, attention).
- Benchmark a small-scale inference job on Nvidia H100 and Google Ironwood (available via Cloud trial) to capture latency, FLOPs/Watt, and cost per hour.
Quantify the “lock-in” cost.
- Compute the engineering effort needed to port your model from CUDA to XLA or TensorFlow Serving on Ironwood.
- Use the formula: lock-in cost = (dev-hours × hourly-rate) + (software-licensing × years).
Build a “dual-source” proof-of-concept.
- Deploy a replica of your most latency-sensitive micro-service on both Nvidia and Ironwood.
- Capture the 2025-baseline SLAs and cost; if Ironwood shows >15 % lower TCO, flag it for production migration.
Plan for Rapidus risk exposure.
- Since Rapidus’ mass-production window is 2027 ± 2 years, treat it as a “future-proof” option.
- Secure a seat in their early-access program (requires a joint design-manufacturing co-opt).
- Align your silicon-design team with the single-wafer processing flow: use the AI-driven sensor data API that Rapidus publishes for real-time yield feedback.
Mitigate talent bottlenecks.
- Upskill existing engineers on GAA nanosheet design using IBM’s open-source design-kit (available on GitHub).
- Partner with Japanese universities (e.g., the University of Tokyo’s Semiconductor Center) to create internship pipelines.
Finance the gap.
- Estimate the additional capital needed beyond the $6.5 bn subsidy: (total $35 bn − government $6.5 bn = $28.5 bn).
- Explore private-equity vehicles that specialize in “foundry-as-a-service” (e.g., SoftBank Vision Fund).
Track the node-race timeline.
- By 2027, TSMC & Samsung will have been shipping 2 nm products for at least two years; Samsung is already filing patents for a 1.4 nm node slated for 2028.
- Set internal benchmarks to “match or exceed” the 2 nm performance target within six months of the first Rapidus volume lot.
Pitfalls & edge cases
- Funding volatility: The $6.5 bn subsidy covers only a fifth of Rapidus’s planned spend; any shortfall can delay the two-year ramp-up and erode stakeholder confidence.
- Talent scarcity: Japan’s semiconductor talent pool has thinned since the 1990s; hiring senior process engineers now costs ~30 % more than in the US, and the domestic university pipeline cannot meet demand.
- Single-wafer trade-off: While flexible, single-wafer processing reduces overall wafer throughput by up to 30 % compared with traditional batch processes, potentially inflating per-chip cost if demand spikes.
- Analog AI chip hype: Chinese firms claim analog AI chips can be 1,000 × faster than Nvidia GPUs, but real-world precision and scalability remain unproven — expect limited early-adoption.
- Closed ecosystems: Ironwood, Trainium, and Maia remain tightly coupled to their respective clouds; using them in a hybrid or on-prem environment may require expensive bridging layers or data-egress fees.
- EUV supply: With each EUV machine priced > $300 M, a fab that installs > 200 such tools (as Rapidus has done) must secure long-term financing; any delay in tool delivery cascades into yield ramp-up times.
Quick FAQ
- What does “AI chips” really encompass? AI chips are specialized accelerators (GPUs, TPUs, ASICs) optimized for matrix-heavy workloads such as deep-learning inference and training.
- How does single-wafer processing differ from traditional batch processing? Instead of processing many wafers simultaneously on a single track, each wafer is processed independently, allowing on-the-fly tuning but sacrificing batch-throughput.
- Can I run Ironwood workloads on-prem? No. Ironwood is offered exclusively through Google Cloud; on-prem usage would require a separate licensing agreement that Google does not currently provide.
- Is the 2 nm node truly “production-ready” by 2027? Rapidus targets mass-production in 2027, but the node’s commercial viability hinges on meeting yield targets (> 70 %) and closing the $28.5 bn funding gap.
- Will analog AI chips replace digital GPUs for inference? Not in the near term. They excel at ultra-low-latency, energy-constrained tasks but struggle with precision and scaling—making them complementary to digital accelerators.
- How do government subsidies affect the competitive landscape? Subsidies lower the incremental cost for domestic fabs, potentially leveling the playing field against TSMC/Samsung, but they also introduce policy-driven risk if political winds shift.
- What’s the timeline for the next node after 2 nm? Samsung has filed patents for a 1.4 nm process slated for 2028; TSMC is rumored to be exploring sub-1.5 nm gates for 2029.
Conclusion
If you’re a CTO wrestling with a single-vendor dependency on Nvidia, the emerging alternatives are not just buzzwords—they’re concrete levers you can start pulling today. Begin with small-scale Ironwood trials, map your cost-per-inference, and keep a “dual-source” roadmap that includes a Rapidus 2 nm pilot. Mitigate the talent shortfall by partnering with academia and leveraging IBM’s open GAA design kits. Finally, secure a diversified financing slate that can bridge the $28.5 bn gap before the 2027 deadline; otherwise the two-year window closes, and you’ll be watching TSMC and Samsung pull ahead while your supply chain remains exposed.
Glossary
- AI chip: A processor (GPU, TPU, ASIC) built to accelerate artificial-intelligence workloads.
- TPU (Tensor Processing Unit): Google’s ASIC for matrix math, optimized for inference and training.
- EUV lithography: Extreme-ultraviolet patterning technology used for sub-7 nm nodes; each machine costs > $300 M.
- Nanosheet transistor: A gate-all-around (GAA) transistor with stacked silicon sheets that improves electrostatic control at 2 nm.
- Single-wafer processing: Fabrication method where each wafer is individually processed, enabling custom designs per wafer.
- Design-manufacturing co-optimization: Real-time feedback loop where AI models adjust wafer processing parameters to boost yield.
- Analog AI chip: A circuit that computes inference using continuous voltages or currents instead of digital logic, promising high speed but limited precision.
References
- Nvidia — CNBC (2024). Nvidia dominates the AI chip market, but there’s rising competition. https://www.cnbc.com/2024/06/02/nvidia-dominates-the-ai-chip-market-but-theres-rising-competition-.html
- Google — Ironwood TPU (2025). Ironwood: The first Google TPU for the age of inference. https://blog.google/products/google-cloud/ironwood-tpu-age-of-inference/
- IBM — Rapidus and IBM (2025). Rapidus and IBM move closer to scaling out 2 nm chip production. https://research.ibm.com/blog/rapidus-ibm-move-closer-to-scaling-out-2-nm-chip-production
- Kyodo News — Japanese government to invest (2025). Japanese government to invest 100 bn yen in chipmaker Rapidus. https://english.kyodonews.net/articles/-/65400